No hard numbers, no prototypes, but a whole lot of articulate hopes and dreams. I guess this is what we should come to expect when the industry invests in people over ideas.
So, let's address the elephant in the room; what will this solve? Today, chip design can be solved in highly efficient constraints using Verilog and no AI. Complex ASIC pipelines might benefit from a robot trying to optimize the logic, but I can't see how this would improve on modern RISC or SIMD architectures. If anything, trusting AI to write a "good enough" MVP is an opportunity for enormously inefficient mistakes to make their way into production chips.
Plus the other issue - maybe you can get your AI to out-perform Intel and Apple. But can you muscle your way into TSMC to start fabbing competitive hardware? Your AI-generated x86 chip could have twice the IPC of an AMD chip, but still end up slower if your clients are forced to fab it on 14nm silicon. Same goes for edge hardware - is your solution any cheaper than a Chinese STM-32 using GPIO?
The whole thing seems like a great idea for the 1950s, but a terrible solution to digital computer chip design.
No hard numbers, no prototypes, but a whole lot of articulate hopes and dreams. I guess this is what we should come to expect when the industry invests in people over ideas.
So, let's address the elephant in the room; what will this solve? Today, chip design can be solved in highly efficient constraints using Verilog and no AI. Complex ASIC pipelines might benefit from a robot trying to optimize the logic, but I can't see how this would improve on modern RISC or SIMD architectures. If anything, trusting AI to write a "good enough" MVP is an opportunity for enormously inefficient mistakes to make their way into production chips.
Plus the other issue - maybe you can get your AI to out-perform Intel and Apple. But can you muscle your way into TSMC to start fabbing competitive hardware? Your AI-generated x86 chip could have twice the IPC of an AMD chip, but still end up slower if your clients are forced to fab it on 14nm silicon. Same goes for edge hardware - is your solution any cheaper than a Chinese STM-32 using GPIO?
The whole thing seems like a great idea for the 1950s, but a terrible solution to digital computer chip design.